This invention in general relates to semiconductor memories, and more specifically to a dynamic random access memory (DRAM) made up of stacked memory cells.
Recently, the scale of semiconductor memory integration has increased remarkably. Of all the forms of semiconductor memory, DRAMs require the finest fabrication processing, and it is necessary for DRAMs to have appropriate storage capacitors having the ability of storing sufficient electric charge. Trench memory cells and stacked memory cells are widely used for DRAM. A trench memory cell utilizes a hole formed in a semiconductor substrate for forming a charge-storage electrode. In a stacked memory cell, on the other hand, a charge-storage electrode three-dimensionally "stacks" on a semiconductor substrate. The continuous miniaturization of semiconductor memory dimensions, however, produces problems to the stacked memory cell, such as difficultly in storing a sufficient amount of electric charge. To cope with this problem, charge-storage electrodes must stand high, that is, the height of the charge-storage electrode increases.
In creating required patterns by means of lithography, the depth of focus becomes "shallower" as the limit of resolution becomes lower. Generally, the limit of resolution varies with the wavelength of a light source used, and varies inversely with the numerical aperture of a lens used in the lithographic exposure tool. Therefore, in order to create fine patterns, it is necessary either to use a light source with a shorter wavelength or to increase the numerical aperture of a lens.
The depth of focus, on the other hand, varies with the wavelength of a light source, and varies inversely with the square of the numerical aperture of a lens. This means that the depth of focus becomes shallower as the limit of resolution becomes lower. Therefore, it is necessary to planarize the semiconductor substrate so as to form a fine pattern.
Referring now to FIGS. 16 and 17, the fabrication of a conventional DRAM employing stacked memory cells is described.
FIGS. 16 and 17 each illustrate in cross section a step of the fabrication of a conventional stacked memory cell type DRAM. As shown in FIG. 16, an insulator layer 2 for isolation between devices is formed on a p-type semiconductor substrate 1. Then, a gate insulator layer 4 constituting a switching transistor and a gate electrode 5 (i.e. a word line) are formed. Next, a bit line 6 is formed in an n-type diffused layer 3 provided on one side of the gate electrode 5, and an insulator layer 20 is formed all over the semiconductor substrate 1. Thereafter, a contact hole 20a is formed in the insulator layer 20 down to an n-type diffused layer 3 provided on the other side of the gate electrode 5 and then a charge-storage electrode 7 of p-doped polysilicon is formed in the same n-type diffused layer 3.
As shown in FIG. 17, a capacitor insulator layer 8, made up of a silicon nitride layer and a silicon dioxide layer, is formed on the charge-storage electrode 7 and on the insulator layer 20, and a plate electrode 9 is formed on the capacitor insulator layer 8. A BPSG film 10 (i.e., an interlayer insulator) is deposited on the plate electrode 9. The BPSG film 10 is subjected to a heat treatment. The BPSG film 10 reflows upon heating. In this way, the BPSG film 10 is planarized.
In spite of such a planarization process, there still exists an absolute level difference 15 between a memory cell array region 40 and a peripheral circuit region 30 of the semiconductor substrate 1. The absolute level difference 15 agrees with the sum of the charge-storage electrode's 7 height and the plate electrode's 9 film thickness. It is said that a 64M DRAM requires a storage capacitor with a capacitance of about 30 fF. Therefore, for the case of a memory cell array with an area of 1.5 .mu.m.sup.2, the charge-storage electrode 7 must stand about 800 nm if a capacitor insulator layer equivalent to a 6-nm silicon dioxide layer is used.
The above-described organization presents some problems. For example, if a 200-nm polysilicon layer as the plate electrode 9 is used, this creates, between the memory cell array region 40 and the peripheral circuit region 30, a steep side 35 causing about 1 .mu.m of level difference equivalent to the sum of the charge-storage electrode's 7 height and the plate electrode's 9 film thickness. As a result, the formation of wiring patterns at later stages becomes difficult. A 64M DRAM requires 0.35-.mu.m pattern formation. However, the depth of focus becomes shallower as required patterns become finer, when photolithography is used. In other words, it is difficult to form a fine pattern on the steep side 35.
FIG. 18 shows in cross section a step. A contact hole 16 is formed which passes through the insulator layer 20 and the BPSG film 10. Then, a tungsten 17 is deposited on the entire surface of the BPSG film 10, as a result of which the contact hole 16 is filled with the tungsten 17. The tungsten 17 deposited on the surface is etched back so that the tungsten 17 remains only in the contact hole 16.
The tungsten 17 is deposited in a perpendicular direction to the BPSG film 10. The film thickness (t.sub.2) of the tungsten 17 at the steep side 35, measured in a perpendicular direction to the semiconductor substrate 1, can be written t.sub.2 =t.sub.1 /cos.theta. where t.sub.1 is the film thickness of the tungsten 17 at the BPSG film's 10 flat surface and .theta. is the maximum tilt angle (hereinafter called the flow angle) of the steep side 35 defined between the memory cell array region 40 and the peripheral circuit region 30. It is necessary to etch back the tungsten 17 by a proportional amount to the film thickness t.sub.2 in order to remove the tungsten 17 at the steep side 35. That is, the flow angle .theta. increases as the tungsten 17 held in the contact hole 16 is trenched down deeper. This results in the drop in contact reliability.
FIG. 19 shows a resist layer 19 used for patterning a metal layer 19 of Al, Si, and Cu deposited on the BPSG film 10. In FIG. 19, T.sub.1 represents the film thickness of the resist layer 19 at the center of the memory cell array region 40, T.sub.2 represents the film thickness of the resist layer 19 at one end of the memory cell array region 40, and T.sub.3 represents the film thickness of the resist layer 19 at the steep side 35 between the memory cell array region 40 and the peripheral circuit region 30. The differences between T.sub.1, T.sub.2, and T.sub.3 increase as the flow angle .theta. increases. This causes considerable variations in dimensions when patterning the resist layer 19 by photolithography.